Vishnu Chelle
vishnu.chelle@gmail.com | (816)-714-9559 | | | |

Project: Twitter Data Analysis | Aug 2014 - Dec 2014


Technology: Apache Hadoop, Python, GraphLab Create, Pandas, IPython

Developed a system to store, analyze and visualize Twitter data.
Nearly 10million Tweets are streamed and stored in HDFS. Dataset is pulled into GraphLab Create to perform analytics and visualizations.
Used the machine learning toolkits provided by GraphLab to perform analytics like Topic extraction from Tweets, Finding nearest neighbors in the Tweets and Sentiment analysis based on Tweet data.
Project is scripted in Python using the interactive computing tool IPython.
Analytics and visualizations are highly appreciated by department professors.


Project: Product Derivation of a Product Line Application | Aug 2014 - Dec 2014


Technology: Java, Eclipse IDE, ArchStudio4, CIDE, ANTLR

Developed a feature customization tool (code parser) for an existing application with a set of features which allows user to select/unselect a set of features to generate a variant of the source application.
The project was developed following the annotative approach where the source code is annotated and code fragments are mapped with the features.
Provided two solutions for the project. 1) Using the CIDE tool to annotate the code and generate variants. 2) Developed own Java parser generator using ANTLR to generate variants.
Also developed GUI to allow user to select desired features.


Project: Hadoop Scheduling algorithm | Aug 2014 - Dec 2014


Technology: Java, Apache Hadoop, IBM Cloud Instance, Shell script, and ANT script

Made changes in Hadoop source code and implemented our own scheduling algorithms for job scheduling.
Analyzed the performance of each scheduling algorithm with different cluster sizes.


Project: FPGA based advanced planting and sowing machine controller design | Apr 2012


Technology: Verilog HDL, FPGA

Implementation of IEEE paper - FPGA Based Advanced Sowing and Planting Equipment Controller Design.
Developed own state diagram which gives better performance that the proposed one in the IEEE paper.
Programmed in Verilog HDL and implemented in Xilinx Spartan II FPGA kit.